Titanium underlayer for lines in semiconductor devices

ABSTRACT

A thin Titanium underlayer  22  is included beneath a Titanium rich Titanium Nitride layer  28  in a metal line  20  on a silicon substrate to reduce stress voiding.

FIELD OF THE INVENTION

The present invention relates to the use of a Titanium (Ti) underlayer,together with a Titanium rich Titanium Nitride (Ti rich TiN) layer. Moreparticularly it relates to the use of such layers with metal lines insemiconductor devices

BACKGROUND ART

Metal lines are used in semiconductor devices to connect components orindividual points together. The metal lines are isolated from each otherby dielectrics. A typical interconnect line used in semiconductordevices, for instance as is used in CMOS 18 or CMOS 18 shrink, is shownin FIG. 1. The line 2 consists of a main, conductive metal layer ofaluminium-copper alloy (AlCu layer) 4, with a Ti rich TiN layer 6 aboveand a Ti rich TiN underlayer 8, below.

In an alternative (not shown), both Ti rich TiN layers are replaced witha TiN layer on top of a Ti layer. Such a combination is, for instanceshown in published patent document EP-A-0,875,923. According to thatdocument, it is critical that the bottom Ti underlayer has a thicknessof from about 90 to about 110 Angstroms (10⁻¹⁰ m). It is exemplified bya metal stack as follows:x Å Ti/100 Å TiN/2300 Å Al (0.5% Cu)/50 Å Ti/400 Å TiNwhere there were five different thicknesses x between 30 and 200 (Å).

A similar combination is shown in published patent document U.S. Pat.No. B2-6,346,480, where the exemplified stack is:30 nm Ti/100 nm TiN/450 nm Al—Cu/15 nm Ti/50 nm TiN.

Similar combinations of varying thicknesses are also shown in a numberof other published patent documents, for example: U.S. Pat. No.B1-6,319,727 and U.S. Pat. No. 6,080,657. Other combinations are alsoknown, for instance a TiN or Ti underlayer, beneath a TiAl₃ layer,beneath a main Aluminium layer beneath another TiN or Ti layer.

The intervening dielectrics between such known lines are deposited byway of chemical vapour deposition (CVD) techniques. However, theencapsulating dielectrics subject the metal lines to mechanical tensilestresses, which result in stress induced voids (SIV) in the metal lines.Intrinsically, such dielectrics are compressive films, i.e. the AlCulines which are encapsulated experience tensile stresses. The stressvoids occur as a result of the tensile forces on the grain boundaries.This problem is pronounced when the intermetal dielectric is depositedusing high density plasma (HDP) methods, as such materials are known toimpart large tensile stresses on the metal lines.

The tensile stresses are also increased when the coefficient of thermalexpansion (CTE) between the AlCu interconnect metal lines differ. Thus,when the semiconductor device experiences thermal cycles during itslifetime, the tensile stresses induced on the metal lines are largeenough to cause SIVs.

Typically SIVs are wedge shaped voids in the metal lines. Suchvoids/cracks occur where the yield stress is lowest, which is at thegrain boundaries of the metal interconnect lines. In general, themethodology for evaluating such voids is by subjecting the completedsemiconductor devices to a period of thermal stress and then checkingfor SIVs by delayering away the passivating dielectrics and inspectingunder a scanning electron microscope (SEM). Typical stress voids arewedge shaped and occur at the grain boundaries where the yield stress islowest. FIGS. 2A and 2B show two views of three AlCu metal interconnectlines 2 after the passivating dielectrics are removed. FIG. 2A is a topplan view and FIG. 2B an isometric view. A stress induced void 10 isclearly present on one of the lines, being approximately 300 nm long and100 nm across the width of the line (about one third of the width of theline). However, the voids can be any size and depth, even to the extentof breaking the metal line.

SIVs in AlCu interconnect lines are a reliability concern, as theincrease in the resistance of the metal line (as a result of the reducedcross sectional area) will result in device failure, either as aconsequence of the increase in the RC time delay constant or because ofstructural failure if the metal opens. If a fabrication plant is unableto control or avoid such voids, it is unable to obtain suitablequalification for production of relevant devices.

SUMMARY OF THE INVENTION

It is an aim of the present invention to provide a new metal line.Ideally it would at least partially alleviate the problems with theprior art and reduce the presence of stress voids.

According to one aspect of the present invention, there is provided aconductive line for a semiconductor device including: a first conductivelayer; a Titanium layer; and a first Titanium rich Titanium Nitridelayer between the first conductive layer and the Titanium layer.

The invention also provides a silicon substrate having a plurality ofsuch conductive lines thereon.

According to another aspect of the present invention, there is provideda process for manufacturing a conductive line, comprising the steps of:depositing a Titanium layer onto a substrate; depositing a firstTitanium rich Titanium Nitride layer to the other side of said Titaniumlayer relative to said substrate; and depositing a first conductivelayer to the other side of said first Titanium rich Titanium Nitridelayer relative to said Titanium layer.

In general terms, the invention is the provision of a Titaniumunderlayer beneath a Titanium rich Titanium Nitride layer in a metalline on a silicon substrate to reduce stress voiding. The Titaniumunderlayer is preferably thin.

The Titanium layer is preferably a 75 Å layer, providing an actualthickness of about 60 to 110 Å.

The invention also provides semiconductor devices, memories andintegrated circuits including one or more such conductive lines.

BRIEF SUMMARY OF THE DRAWINGS

The invention will now be further described, by way of non-limitativeexample with reference to the accompanying drawings, in which:

FIG. 1 is a schematic view of a cross-section of a prior art metal line;

FIGS. 2A & 2B are enlarged views of a prior art set of metal lines, withvarious layers stripped away, showing the presence of a stress inducedvoid;

FIGS. 3A & 3B show different test structures used to test the metallines produced;

FIG. 4 is a schematic view of a cross-section of a metal line of thepresent invention;

FIG. 5 shows the results of X-Ray diffraction analysis of variousmetals; and

FIG. 6 is a TEM picture through an embodiment of the present invention.

SPECIFIC DESCRIPTION

In the following description and elsewhere the thicknesses of variouslayers are given. In relation to the present invention, except whenotherwise indicated, these are nominal thicknesses, based on depositiontime and deposited rate. These may differ from actual thicknesses due todifficulties in obtaining accurate deposits. This is typical in thewafer fabrication business.

The following description relates mainly to a process for producinginterconnect lines for CMOS18 structures. A typical 18 μm (micron)technology integrated circuit has six metal layers, withsilicon-rich-oxide liners and intermetal dielectrics (IMDs) between thelayers. Each metal layer typically consists of an AlCu layer sandwichedbetween Ti or TiN layers. The relative thicknesses for the components ofeach layer can vary through the stack. With layer M1 being the lowermostlayer and layer M6 being the uppermost, the thicknesses of the layers ofa typical current metal stack may be constituted as follows:M1-M4: 250 A Ti rich TiN/4000 A AlCu/250 A Ti-rich TiNM5-M6: 500 A Ti rich TiN/8000 A AlCu/250 A Ti-rich TiN

With the intention of overcoming the SIV problem, the inventors triedvarious experiments, including: varying the use of N₂O during CVD orannealing, varying the etching machine, varying aspects of post etchcleaning, breaking the vacuum between TiN and AlCu deposition, modifyingthe metal strip recipe, modifying the high density plasma recipe, usingsub-atmospheric (SA) CVD for the intermetal dielectric between layers M5and M6 (IMD5) and providing a thicker silicon-rich-oxide liner on themetal line between the metal line and the IMD. None of these worked. Forexample SA CVD is known to impart, intrinsically, compressive stresseson the metal lines, which would prevent metal stress voids. However,SACVD is intrinsically in tension at all times, which makes itsusceptible to cracking

The inventors then tried other approaches, in particular experimentsbased on variation in the Metal 1 level in CMOS 18 to examine metalstack changes and metal deposition temperatures on SIV. It was thoughtthat by modifying the underlying barrier metal or by changing thedeposition temperatures, it could help to change the grain structure ofthe metal lines and/or act as a stress relief layer, so as to reduce thetensile stress on the metal lines. The details of the differentcombinations of materials, their thicknesses and deposition temperaturesare shown in Table 1. TABLE 1 Expt Deposit No. Stack Composition - Allfigures in Å (10⁻¹⁰ m) Temp (° C.) 1a 75stdTi/4000AlCu/250Ti × TN 270 1b450 2a 150stdTi/4000AlCu/250Ti × TN 270 2b 450 3a 250Ti × TN/FlashTi100/4000AlCu/250Ti × TN 270 3b 450 4a 300stdTi/250Ti ×TN/4000AlCu/250Ti × TN 270 4b 450 5a 250Ti × TN/4000AlCu/250Ti × TN 3005b 350 5c 400 5d 450 6a 150ALPS Ti/100TiN/4000AlCu/250Ti × TN 270 6b250ALPS Ti/100TiN/4000AlCu/250Ti × TN 270 6c 250ALPSTi/100TiN/4000AlCu/250Ti × TN 270 6d 300ALPS Ti/100TiN/4000AlCu/250Ti ×TN 270 6e 300ALPS Ti/100TiN/4000AlCu/250Ti × TN 450 7 160IMP Ti/70CVDTiN/4000AlCu/250Ti × TN 270 8 160IMP Ti/4000AlCu/250Ti × TN 270where“std”: pure Ti that is deposited by standard Physical Vapour deposition(PVD) methods.“Flash”: another name referring to pure Ti.“ALPS”: Advanced Low Pressure Sputtering“IMP”: Ionised Metal Plasma“Ti × TN”: Ti-rich Ti-Nitride - The Ti × TN is deposited by firstsputter-depositing Ti for a few seconds and then flowing N₂ gas into thechamber to form a TiN layer.

For each experimental stack two different types of structures werecreated, on the same wafer, for different tests. The structures areshown in FIGS. 3A and 3B.

FIG. 3A shows an NIST (National Institute of Standards andTechnology—US) test structure. It is a small elecromigrationExtrusion-type structure, having 3 lines and being 800 μm (microns)long, with a pattern density (PD) of about 48%.

FIG. 3B shows a second, yield module (YM) test structure, with a large,comb meander-type structure, with metal layers M1 to M4 having a topsurface area of 6.66 mm² and metal layers M5 to M6 having a top surfacearea of 20 mm², with a PD of about 50%. This is a typical type of metalstructure that can be expected in an integrated circuit.

To be acceptable the results from a production process must pass a poststress SIV visual inspection on a sample from each layer. The inspectionrequires that the wafer be stressed, for instance by keeping at 200° C.for 24 hours. The passivation layer and the IMD layers are removedthrough delayering and reactive ion etching (RIE) to expose all themetal lines. This is followed by a visual inspection of design rulestructures in a SEM. For both NIST and the second (YM) tests, thenecessary criteria for passing are shown in Table 2. TABLE 2 Stress voidsize (as % of width of metal line) Criteria 10-25% <30 voids/cm 25-50%<10 voids/cm   >50%    0 voids/cm

The results of the two tests on the various experimental stacks areshown in Table 3. TABLE 3 Expt YM NIST No. 10-25% 25-50% >50% 10-25%25-50% >50% 1a 375 0 0 525 112.5 0 2a 4375 875 0 462.5 125 0 2b 100001500 0 1875 575 0 3a 17500 15000 0 2000 1262.5 0 3b 4250 875 0 1137.5925 50 4a 0 0 0 35 0 0 4b 0 0 0 62.5 12.5 0 5a 0 0 0 37.5 12.5 0 5b 0 00 500 200 0 5c 0 0 0 225 0 0 5d 0 0 0 12.5 0 0 6a 625 1250 0 125 45037.5 6b 875 375 0 12.5 0 0 6c 1000 500 0 0 0 0 6d 1500 625 0 225 500 1256e 1125 500 0 125 112.5 0 7 250 0 0 150 0 0 8 2500 125 0 2250 450 0

The actual counts were conducted over 80 μm (microns) and the resultsmultiplied up by 12.5.

Thus experimental stack No. 5a passes all the criteria for the YM teststructure, but fails one of them for the NIST structure. In particular,there are 37.5 voids/cm along the metal line whose size is between10-25% of the width of the metal line. This is greater than the 30voids/cm allowed. There are also 12.5 voids/cm whose size is between25-50% of the width of the metal line. This is greater than the 10voids/cm allowed.

Stack 1b was not tested as stack 1a did not work and it was deemedpointless to consider stack 1b.

From the results, it can be seen that experiment No. 4a (300 A Tiunderlayer beneath the current metal stack) shows some of the mostpromising results. From this table other layers would also appear to bepromising, but were not useful for other reasons. For instance, stack 5dwas not considered because it was not compatible with the IMD being,which was a fluorinated silicate glass (FSG). At a high temperature of450° C., the fluorine would outgas and (among other things) causecorrosion to the metal lines.

Further experiments were then necessary to determine the optimalthickness of the Ti underlayer. New stacks were produced, with a Tiunderlayer deposit at different temperatures and different thicknessesbeneath a 250Ti×TN/4000Al/250Ti×TN stack, as shown in Table 4. TABLE 4Deposit Ti Underlayer Thickness Expt Temp. ° C. Angstroms (10⁻¹⁰ m) No.100 150 0 75 150 200 300 450 11 X X 12 X X 13 X X 14 X X 15 X X 16 X X17 X X 18 X X

The maximum nominal thickness is a 450 Å Ti underlayer. Typically thismight lead to a physical thickness of up to 500 Å. The thinnest layertried was 75 Å (nominal). Thinner layers may be possible but becomeincreasingly difficult to achieve.

The visual SIV results for these experiments are shown in Table 5 TABLE5 Expt YM NIST No. Yield % 0-25% 25-50% >50% 0-25% 25-50% >50% 11 82.5 00 0 0 0 0 12 75.9 0 0 0 12.5 0 0 13 74.7 0 125 0 25 0 0 14 69.3 0 0 0 00 0 15 65.7 0 0 0 25 0 0 16 71.7 0 0 0 0 0 0 17 63.3 0 0 0 0 0 0 18 68.10 0 0 62.5 0 0

Completed wafers were tested electrically. The yield indicated in Table5 is the number of passing integrated circuits (ICs) compared to thetotal number of ICs, given as a percentage.

Thus the clearest results are from experiments 1, 4, 6 and 7. However,of these the highest yield was achieved in experiment no. 11. Thisexperiment shows that a 75 Å Ti underlayer deposited at 150° C. issufficient to improve the SIV substantially. It is generally desired forthe Ti thickness to be as thin as possible to reduce deposition time andto reduce the impact for the metal etch process. Lower productiontemperatures are also preferred, mainly for fear of the fluorineoutgassing from the FSG. It is also desirable to reduce the thermalbudget for the transistors, which may show some drift in characteristicswhen the thermal budget changes.

An interconnect line of the present invention to be used insemiconductor devices, for instance in CMOS 18 or CMOS 18 shrink, istherefore shown in FIG. 4. This is at least nominally similar incross-section to the line of FIG. 1, differing in the addition of the Tiunderlayer 22, and the result it has on the other layers. The line 20thus consists of a main, conductive metal layer of aluminium-copperalloy (AlCu layer) 24, with a Ti rich TiN layer 26 above and a Ti richTiN underlayer 28, below, and a Ti layer 22 lowermost.

Further experiments were conducted to qualify the extra 75 Å Tiunderlayer. Metal lines were deposited on a number of wafers, in NISTtest structures, using different amounts of DC power. One lot wasdeposited at 1500 W and another at 2000 W. The difference that thismakes is in the deposition rate. The higher the DC power, the faster thedeposition rate. From a process point of view, 1500 W Ti is preferredover 2000 W Ti due to better thickness control. The lower powerrequirement allows better process tuning and control of thickness. Theconstruction of lines on each wafer involved metal layer deposit,followed by standard photolithography and standard etching for each oflayers M1-M6. Table 6 shows the structure of each layer TABLE 6 M1-M4Deposit 75 Å Ti 250 Å Ti × TN 4000 Å AlCu 250 Å Ti × TN SiON depositM5-M6 Deposit 75 Å Ti 500 Å Ti × TN 8000 Å AlCu 250 Å Ti × TN SiONdeposit

The SIV visual inspection results for a 1500 W Ti recipe wafer is shownin Table 7. This was post stressing at 200° C. for 24 hours. TABLE 7Total No. of Voids in Stress void size (as % Metal Layers/cm Maximum ofwidth of metal line) M1 M2 M3 M4 M5 M6 Allowed 10%-25% 4 0 4 0 0 0 30/cm25%-50% 4 0 0 0 0 0 10/cm >50% 0 0 0 0 0 0  0/cm

The SIV visual inspection results for a 2000 W Ti recipe wafer is shownin Table 8. This was post stressing at 200° C. for 24 hours. TABLE 8Total No. of Voids in Stress void size (as % Metal Layers/cm Maximum ofwidth of metal line) M1 M2 M3 M4 M5 M6 Allowed 10%-25% 0 13 0 0 0 030/cm 25%-50% 0 4 0 0 0 0 10/cm >50% 0 0 0 0 0 0  0/cm

In this case, the M2 layer is the worst due to experimental variation.

As can be seen by comparing the results with the maxima in the lastcolumn in each of Tables 7 and 8, all SIV visual criteria are met forboth Ti underlayer recipes.

A yield study was conducted with several of the wafers. There was nostatistical difference in the yield between the two recipes for Tiunderlayer deposit.

Metal sheet resistances were also compared against baseline lots.Comparison of the sheet resistances with baseline lots for three monthsshowed that the addition of the 75 Å Ti underlayer did not affect thesheet resistance of the metal lines for thin and thick metal lines.

In order to know the effects of the extra 75 Å Ti underlayer on metaletch on metal bridging and continuity, separate window checks were done.The main conclusion from the window experiments is that the currentmetal etch for CMOS18 and CMOS18 Shrink would be able to cope with theextra 75 Å Ti without any amendments to the etch recipe. The metalcontinuity and bridging of the metal lines would not be affected by theextra 75 Å Ti.

The main conclusions from these experiments are as follows:

-   -   i. SIV are reduced with the inclusion of an addition 75 A Ti        underlayer    -   ii. SIV visual inspection results are equivalent for SP and ST        recipes    -   iii. Yield results are statistically equivalent for both split        legs    -   iv. Metal sheet resistances are unaffected by the inclusion of        the extra 75 Å Ti underlayer    -   v. The current metal etch would be able to cope with the extra        75 Å Ti with no deterioration in metal continuity and bridging.

X-RAY Diffraction (XRD) analysis was performed to seek to determine thecrystal orientation with the addition of the 75 Å Ti underlayer and theresults are shown in FIG. 5. Compared with standard thin metal (i.e. theconventional layer with 4000 Å AlCu), thin metal with the Ti-underlayerbecomes almost fully (220) orientated, and the (111) and (311)orientations become suppressed. Compared with standard thick metal (i.e.the conventional layer with 8000 Å AlCu), thick metal with theTi-underlayer has more grains with (311) and (111) orientation.

To understand the physical thickness of the 75 Å Ti underlayer, aTransmission Electron Microscope (TEM) was used to provide a picture ofthe cross-section of a (thick) metal M5 layer, with the result shown inFIG. 6 for the lower part of the metal layer. The physical thickness ofthe 75 Å Ti underlayer is about 100 Å. This apparent difference isbecause the described thicknesses are actually calculated based ondeposition time and deposited rate and may therefore vary from what isactually deposited. This is typical in the wafer fabrication business.Thus the physical thickness of a 75 Å layer may, in fact be betweenaround 60 to 110 Å.

One hypothesis for the reason the invention works is that theimprovement is a result of a change in the grain orientation of themetal lines (in particular the main metal, exemplified by AlCu), therebyincreasing the resistance of the metal lines to stress migration and/orvoid nucleation resulting in better resistance to SIV. Anotherhypothesis is that the Ti underlayer has a coefficient of thermalexpansion (CTE) in between the intermetal dielectric and the AlCu lines,which results in the Ti underlayer acting as a stress buffer layer.

Although the invention has been exemplified with layers of variousspecific thicknesses, the invention is not limited to these. Althoughmost test were conducted with a 75 Å Ti underlayer, other thicknessesfor the Ti underlayer would also work. (as is shown in the results inTable 5 above). Other thicknesses of Ti×TN also work (as is shown. inthe results in Tables 7 and 8 above). Other thicknesses of some of theother layers would also be expected to work.

Whilst the present invention has been exemplified by a AlCu metal line,it also covers lines of other metals and alloys, in particular otherAluminium alloys (for example with magnesium, silicon, a lanthanide orpalladium).

Thus the present invention provides an improved product and processbased on the addition of an extra Ti layer below a Ti rich TiN layer ina conductive line.

1. A conductive line for a semiconductor device including: a firstconductive layer; a Titanium layer; and a first Titanium rich TitaniumNitride layer between the first conductive layer and the Titanium layer.2. A conductive line according to claim 1, wherein the first conductivelayer is in direct contact with the first Titanium rich Titanium Nitridelayer.
 3. A conductive line according to claim 1, wherein the Titaniumlayer is in direct contact with the first Titanium rich Titanium Nitridelayer.
 4. A conductive line according to claim 1, wherein the firstconductive layer is a metal layer.
 5. A conductive line according toclaim 4, wherein the first conductive layer is an aluminium alloy.
 6. Aconductive line according to claim 5, wherein the aluminium alloy is analuminium copper alloy.
 7. A conductive line according to claim 1,wherein the Titanium layer is less than about 500×10⁻¹⁰ (500 Angstroms)thick.
 8. A conductive line according to claim 7, wherein the Titaniumlayer is from about 60-110×10⁻¹⁰ m (60-110 Angstroms) thick.
 9. Aconductive line according to claim 1, wherein the first Titanium richTitanium Nitride layer is a 250-500×10⁻¹⁰ m (250-500 Angstroms) layer.10. A conductive line according to claim 1, wherein the first conductivelayer is a 4000-8000×10−10 m (4000-8000 Angstroms) layer.
 11. Aconductive line according to claim 1, further comprising a secondTitanium rich Titanium Nitride layer, and wherein the first conductivelayer is between the first and second Titanium rich Titanium Nitridelayers.
 12. A process for manufacturing a conductive line, comprisingthe steps of: depositing a Titanium layer onto a substrate; depositing afirst Titanium rich Titanium Nitride layer to the other side of saidTitanium layer relative to said substrate; and depositing a firstconductive layer to the other side of said first Titanium rich TitaniumNitride layer relative to said Titanium layer.
 13. A process accordingto claim 12, wherein the Titanium layer is deposited directly onto saidsubstrate.
 14. A process according to claim 13, wherein the firstTitanium rich Titanium Nitride layer is deposited directly onto saidTitanium layer.
 15. A process according to claim 13, wherein the firstconductive layer is deposited directly onto said first Titanium richTitanium Nitride layer.
 16. A process according to claim 12, furthercomprising the step of depositing a second Titanium rich TitaniumNitride layer to the other side of said first conductive layer relativeto said first Titanium rich Titanium Nitride layer.
 17. A processaccording to claim 12, wherein the first conductive layer is a metallayer.
 18. A process according to claim 17, wherein the first conductivelayer is an aluminium alloy.
 19. A process according to claim 18,wherein the aluminium alloy is an aluminium copper alloy.
 20. A processaccording to claim 12, wherein the Titanium layer is less than about500×10−10 m (500 Angstroms) thick.
 21. A process according to claim 20,wherein the Titanium layer is from about 60-110×10−10 m (60-110Angstroms) thick.
 22. A process according to claim 12, wherein the firstTitanium rich Titanium Nitride layer is a 250-500×10−10 m (250-500Angstroms) layer.
 23. A process according to claim 12, wherein the firstconductive layer is a 4000-8000×10−10 m (4000-8000 Angstroms) layer. 24.A silicon substrate having a plurality of conductive lines according toclaim 1 thereon.
 25. A semiconductor device including one or moreconductive lines according to claim
 1. 26. A memory including one ormore conductive lines according to claim
 1. 27. An integrated circuitincluding one or more conductive lines according to claim 1.